In mobile communications, demodulation using synchronous detection (quasi-synchronous detection) requires, in addition to a carrier recovery circuit, highly efficient circuits for frequency deviation compensation and for bitclock recovery in order to achieve an accurate carrier recovery.
When a carrier recovery circuit, a frequency deviation compensation circuit, and a bitclock recovery circuit each use a loop filter, the value of a time constant to be used for the loop filter is selected so that an output result from the loop filter becomes an optimum value of convergence.
In a receiving section of radio communication, when a received frame (slot) is asynchronous, then it is desirable to have quick pull-in. A small value is therefore suitable of the time constant. When a received frame is synchronous, then there is no need for having quick pull-in. It is then desirable to improve the accuracy of convergence value of pull-in. A large value is therefore suitable of the time constant in order to have a longer duration of averaging.
If each loop filter is provided with a single value of a time constant, then an output result from the loop filter does not become an optimum convergence value, particularly in a reception process of radio communications involving such a transition from an asynchronous state to a synchronous state. This is because an optimum value of a time constant required for the filter depends on whether a received frame (slot) is synchronous or asynchronous.
A system described in “Multiple Signal Reproducing Device” (Unexamined Patent Publication Number Hei07-336325) shows an example of a demodulator, which switches time constants according to the reception state, synchronous/asynchronous, thereby achieving highly efficient demodulation.
According to this system, the demodulator is equipped with a loop filter. Different values of time constants are then provided to correspond to the two states of a synchronous state and an asynchronous state. Thus the time constants are switched according to the state.
The above-mentioned system, however, does not relate to a receiving device for receiving a phase-modulated burst signal used for radio communications. In addition to this, the system does not have the objective of improving receiver sensitivity in radio communications where a phase-modulated burst signal is demodulated by a synchronous detection system (or a quasi-synchronous detection system).
“Control Method for Radio Communication Device and Radio Communication Device” (Unexamined Patent Publication Number 2003-209485) is configured to have a plurality of time constants and filters each provided for each time constant, so that an optimum value of an filter output can be selected. This has the effect that an output value of a filter using an optimum time contestant is always selected.
Such an approach to have a filter circuit corresponding to each time constant, however, requires as many filters using time constants as the number of the time constants. This results in an increase in the size of a circuit.
The TDMA-TDD system in mobile communications requires highly accurate performance in frequency deviation compensation, carrier recovery, and bitclock recovery when a synchronous detection system (or a quasi-synchronous detection system) is employed as a demodulation system of a demodulation section in a receiving unit for receiving a phase-modulated burst signal. Functional blocks for frequency deviation compensation, carrier recovery, and bitclock recovery each require a loop filter for averaging, sequential computing, etc., so that sufficient performance cannot be expected if only one type of a time constant is multiplied in the loop filter.
With a demodulation section that is equipped with a loop filter circuit and performs synchronous detection (or quasi-synchronous detection) based on the TDMA-TDD system, when a burst signal has changed from asynchronous to synchronous, if the size of the time constant is unchanged or a rapid change is made in the size of the time constant from a small value for an asynchronous state to a large value for a synchronous state, then jitter after convergence cannot be minimized and quick pull-in cannot be achieved.    Patent Document 1: Unexamined Patent Publication No. Hei 7-336325    Patent Document 2: Unexamined Patent Publication No. 2003-209485